Interrupt Status Register
| TX_THLD_STS | Transmit Buffer Threshold Status The interrupt is generated when the number of empty locations in transmit buffer is greater than or equal to threshold value specified in I3C_DATA_BUFFER_THLD_CTRL[TX_EMPTY_BUF_THLD] field. This bit is cleared automatically when number of empty locations in transmit buffer is less than specified threshold value. |
| RX_THLD_STS | Receive Buffer Threshold Status The interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified in I3C_DATA_BUFFER_THLD_CTRL[RX_BUF_THLD] field. This bit is cleared automatically when number of entries in receive buffer is less than specified threshold value. |
| IBI_THLD_STS | IBI Buffer Threshold Status This bit is only used in Master mode of operation. The interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified in I3C_QUEUE_THLD_CTRL[IBI_BUF_THLD] field. This bit is cleared automatically when number of entries in IBI buffer is less than specified threshold value. |
| CMD_QUEUE_READY_STS | Command Queue Ready The interrupt is generated when number of empty locations in command queue is greater than or equal to threshold value specified in I3C_QUEUE_THLD_CTRL[CMD_EMPTY_BUF_THLD] field. This bit is cleared automatically when number of empty locations in command buffer is less than specified threshold value. |
| RESP_READY_STS | Response Queue Ready Status The interrupt is generated when number of entries in response queue is greater than or equal to threshold value specified in I3C_QUEUE_THLD_CTRL[RESP_BUF_THLD] field. This bit is cleared automatically when number of entries in response buffer is less than specified threshold value. |
| TRANSFER_ABORT_STS | Transfer Abort Status This bit is used only in Master mode of operation. The interrupt is generated if transfer is aborted. This interrupt can be cleared by writing 0x1. |
| CCC_UPDATED_STS | CCC Table Updated Status This bit is used only in Slave mode of operation. The interrupt is generated if any of the CCC registers are updated by I3C master through CCC commands. This interrupt can be cleared by writing 0x1. |
| DYN_ADDR_ASSGN_STS | Dynamic Address Assigned Status This bit is used only in Slave mode of operation. The interrupt is generated if the device Dynamic address is assigned through SETDASA or ENTDAA CCC. This bit can be cleared by writing 0x1. |
| TRANSFER_ERR_STS | Transfer Error Status The interrupt is generated if any error occurs during transfer. The error type is specified in the response packet associated with the command in ERR_STATUS field. The error type is specified in the response packet available in I3C_RESPONSE_QUEUE_PORT[RESPONSE] as per the value in ERR_STATUS field . This bit can be cleared by writing 0x1. |
| DEFSLV_STS | Define Slave CCC Received Status The interrupt is generated if DEFSLV CCC is received. This bit can be cleared by writing 0x1. |
| READ_REQ_RECV_STS | This bit is used only in Slave mode of operation. Read request received from the current master when CMDQ is empty. This bit can be cleared by writing 0x1. |
| IBI_UPDATED_STS | This bit is used only in Slave mode of operation. It indicates that the IBI request initiated through SIR request register is addressed and status is updated. |
| BUSOWNER_UPDATED_STS | This interrupt is set when the role of the I3C changes from being a Master to Slave or the opposite. This bit can be cleared by writing 0x1. |
| BUS_RESET_DONE_STS | Bus Reset Pattern Generation Done Status This bit is used only in Master mode of operation. The interrupt is generated when the SCL Low Timeout Bus Reset Pattern Generation is completed. This bit can be cleared by writing 0x1. |